Some processors may allow simultaneous read and write operations to be performed on a memory structure such as a cache, in order to increase the number of instructions processed per cycle. However, hazards may arise when simultaneous read and write operations are scheduled on the same memory entry, such as the same cache line. These hazards may not only result in functional errors, but may also lead to harmful conditions such as crowbar currents, which may cause severe damage to the memory structure. Particularly, for memory structures such as static random access memory (SRAM), when read and write drivers to the same SRAM bit cell are enabled, read/write circuitry such as cross-coupled bitline keepers may be confused by opposing currents, which can give rise to harmful crowbar currents and drive the cross-coupled bitline keepers to a meta-stable state.
An illustration of the above scenario will be provided with respect to FIG. 1A. In FIG. 1A, a conventional fully differential SRAM array 100 is illustrated. SRAM array 100 includes bit cells 102i, 102j, etc, each configured as a ten transistor (10T) SRAM cell as is known in the art. Write word lines WWL 104i and WWL 104j are enabled (i.e. driven to a high voltage level or logic state) for write operations on corresponding bit cells 102i and 102j. The data to be written is supplied by complementary write bitlines WBL 114a and WBLB 114b. Similarly, read word lines RWL 106i and RWL 106j are enabled for read operations on corresponding bit cells 102i and 102j), and the read data is read out of the corresponding bit cells on complementary read bitlines RBL 116a and RBLB 116b. Transistors 110a-b are used to provide pre-charge clock 110 to SRAM array 100. Cross-coupled bitline keepers 108a and 108b are provided to accelerate the operations on the bit cells. For example, to enable faster reading of bit cells during operations such as tag compares, cross-coupled bitline keepers 108a-b are provided, to mitigate delays in the critical path. However, when simultaneous read and write operations are allowed to take place on the same bit cell, for example, bit cell 102i by enabling both WWL 104i and RWL 106i, cross-coupled bitline keepers 108a-b are driven to a meta-stable state and complementary read bitlines RBL 116a and RBLB 116b are caused to float. This creates a harmful and undesirable crowbar for short-circuit) current to flow through downstream logic 112a-b. Downstream logic 112a-b can include any logic, circuitry, or buses which can be internal or external to SRAM array 100, and it is important to protect downstream logic 112a-b from frequent and potentially irreparable damage which can be caused from the crowbar current.
Existing techniques to prevent crowbar current arising from simultaneous or clashing read and write operations on the same bit cell, include preventing one of the read or the write operations from taking place, in the absence of a write buffer, the write operation cannot be prevented, or otherwise there is a risk of permanently losing the data which was meant to be written. Therefore, in conventional techniques, the read operation is prevented, for example, by suppressing read word line RWL 106i from being enabled or driven to a high state when WWL 104i and RWL 106i are likely to conflict. However, RWL 106i cannot be simply prevented from being enabled because doing so may cause complementary bitlines RBL 116a and RBLB 116b to float. Since complementary bitlines RBL 116a and RBLB 116b are required to be evaluated to complementary logic states when the read circuitry is activated, causing them to float may nevertheless give rise to crowbar current.
Alternative approaches to avoiding the above-described problem include detecting the problematic simultaneous read-write situation well in advance, and sidestepping the problem, for example, by implementing a software fix. For example, the instructions being executed on a processor associated with the memory structure can be reordered to avoid read-write collision hazards. However, such detection and collision prevention in software is not feasible or is impractical because a programmer may not have sufficient visibility into the physical memory locations and/or may lack control over read/write operations as they perform to real time applications. Moreover, software intervention on this level may severely slow down high performance processing applications. The problem is further complicated when multiple processors share the same memory structure. Existing approaches often rely on expensive and inefficient solutions, such as dedicated write buffers, in an attempt to handle situations where read-write collisions may take place. Moreover, to the extent these approaches exist in the general area of handling read-write hazards or collisions, there is continuing need in the art for effectively preventing crowbar currents from arising when a situation does arise in a memory structure, such as a SRAM array, when read and write word lines to a bit cell are simultaneously enabled.